performance

Pipeline and Buses: Parallelism and Communication in the CPU

2026-04-23·4944 words·24 mins

Computer Architecture pipeline buses hardware performance CPU

An assembly line does not wait for one car to be finished before starting the next, and the pipeline does the same with instructions. We will see the stages, the hazards that stall the line, the speedup calculation, the buses that connect CPU, memory, and peripherals, and the control unit.

Cache Memory: Mapping, Replacement, and Writing

2026-04-14·4053 words·20 mins

Computer Architecture cache hardware performance

With a 95% hit rate, the cache makes the processor see a 4.95 ns memory where DRAM takes 80 ns. We will see why it works (locality), the direct, associative, and set-associative mappings, the replacement algorithms, and the write policies.

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