An assembly line does not wait for one car to be finished before starting the next, and the pipeline does the same with instructions. We will see the stages, the hazards that stall the line, the speedup calculation, the buses that connect CPU, memory, and peripherals, and the control unit.
A hypothetical 12-bit processor with 15 instructions serves as a model for following the complete instruction cycle. We execute LDA and ADD register by register, encode instructions in hexadecimal, and write assembly programs with branches and loops.
A 2 GHz processor can execute more instructions per second than a 3 GHz one. To understand why, we open up the CPU: ALU, control unit, registers, flags, decoder, and clock, along with the microevents of the fetch cycle in formal notation.
You press Enter and the result shows up three tenths of a second later. In that interval, the processor fetched hundreds of millions of instructions from memory. This series of 13 articles explains how: memory, cache, CPU, pipeline, data representation, and program execution.
