CPU: Components, Instruction Cycle, and What Happens Inside the Processor

In the previous two articles, we built the foundation of the memory system: the memory hierarchy that organizes DRAM, SRAM, and secondary storage, and the cache that acts as a buffer between the processor and main memory. Now we reach the heart of the system: the Central Processing Unit (CPU).

The CPU is the component that actually computes: it performs arithmetic operations, makes logical decisions, fetches instructions from memory, and coordinates all the other subsystems. Modern processors are manufactured on a single chip, with billions of transistors, and operate at gigahertz frequencies. But the essence of the CPU remains the same as in the first computers: fetch an instruction, decode it, and execute it, over and over, until the system is turned off.

In this article you will learn:

• what the two basic functions of the CPU are and what it accomplishes in terms of primitive operations;
• what a machine instruction is and how it is structured in bits;
• which components make up the CPU and what role each one plays;
• what status flags are and why they exist;
• how the clock synchronizes everything and why frequency is not a synonym for performance;
• the microevents of the fetch cycle in RTL notation;
• the differences between CISC and RISC architectures.

The CPU in the real world

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The CPU is the component that actually executes instructions, processes data, and coordinates the operation of the system. In current computers, it usually comes in a single package connected to the motherboard, although internally it may contain one or more silicon dies, besides caches and specialized functional units.

Despite the enormous physical evolution (billions of transistors, gigahertz frequencies, and multiple cores), the fundamental idea remains the same: fetch an instruction, decode it, and execute it.

What the CPU does

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The CPU has two fundamental functions:

1. Data processing: performing arithmetic operations (add, subtract, multiply, divide), logical operations (AND, OR, XOR), data movement, branches, and input/output operations.
2. Control: coordinating the operation of all the components of the system (main memory, I/O devices, and the other subsystems).

In practice, every complex computation is decomposed into primitive operations: add, subtract, move data between storage locations, transfer data to output devices. A compiler, when processing an expression such as X = A + B*C, generates a sequence of primitive instructions that the CPU executes one by one:

T = B * C    ; 1st instruction
X = A + T    ; 2nd instruction

The CPU never sees the high-level expression: only the elementary instructions that the compiler produced from it.

The figure below shows a simplified diagram of the CPU, highlighting its main components and how they connect to main memory. Note that the CPU is a complex system, but we can understand its basic organization from its functional blocks and the data and control flows between them.

We will detail these components throughout the article, but first we need to understand what a machine instruction is.

Machine instructions

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A machine instruction is a sequence of bits that encodes exactly what the CPU must do. It has two main fields:

• Operation code (Opcode): specifies which operation to execute
• Operands: the data to operate on or the addresses from which to obtain them

For example, a 12-bit instruction with 4 bits for the opcode and 8 bits for the operands could be structured like this:

| Opcode (4 bits) | Operand 1 (4 bits) | Operand 2 (4 bits) |
     0  1  0  1       0  0  0  1            0  0  1  0

The operation above could, for example, represent ADD R1, R2: add the values of registers R1 and R2 and store the result in an implicit destination register (such as the ACC).

With \(n\) opcode bits, we have \(2^n\) possible operations. With 4 bits, for example, we get \(2^4 = 16\) distinct operations.

Word size and registers

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In classic architectures, the processor’s word size usually coincides with the width of the general-purpose registers and with the number of bits handled at once by the ALU. This does not mean, however, that all the CPU’s registers necessarily have the same width.

Specialized registers can have different sizes, according to their function. For example:

• the PC and the MAR follow the size of the address;
• the MDR / MBR follows the width of the data transfer with memory;
• the general-purpose registers and the ACC normally follow the processor’s word.

The impact of word size

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Word size directly influences the amount of data the CPU can transfer and process at a time. In a simple example, if two 16-bit values need to be added:

• in a system with an 8-bit word, each value will have to be handled in two parts;
• in a system with a 16-bit word, each value can be handled at once.

This does not mean that a processor with a larger word will always be exactly twice as fast, but it helps us understand why architectures with larger words tend to reduce the number of accesses and steps needed for certain operations.

To add \(A = \text{3A25}_{16}\) and \(B = \text{172C}_{16}\) (16-bit values):

This explains the historical evolution: from 8- and 16-bit processors to the 32- and 64-bit ones found today in any personal computer or smartphone.

CPU components

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Internally, the CPU is composed of two major functional blocks: the Control Unit (CU) and the Arithmetic Logic Unit (ALU), connected by registers and internal buses.

graph TB
    subgraph UCP["Central Processing Unit"]
        subgraph CTR["Control Unit"]
            REL["Clock"]
            UC["CU — Control Unit"]
            DEC["Decoder (Opcode → operation)"]
            CI["PC — Next instruction"]
            RI["IR — Current instruction"]
            REM["MAR — Address to MM"]
            RDM["MDR / MBR — Data from MM"]
        end
        subgraph PROC["Arithmetic Logic Unit"]
            UAL["ALU"]
            ACC["ACC — Accumulator"]
            REGS["General-purpose registers"]
            FLAGS["Flags Register (N, Z, V, C)"]
        end
        REL --> UC
        UC --> DEC
        RI --> DEC
        DEC --> UAL
        CI --> REM
        RDM --> RI
        UAL <--> ACC
        UAL <--> REGS
        UAL --> FLAGS
    end

    MP[("Main Memory")]

    REM -->|"Address Bus"| MP
    RDM <-->|"Data Bus"| MP
    UC -.->|"Control Bus"| MP

Status flags

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The ALU calculates results and also records properties of the last result in special bits called flags, grouped into what is usually called the status register. These bits are consulted by conditional branch instructions (if, while, etc.) to decide whether the program flow should change.

A well-known historical example is the Motorola 68000 flag set:

This set should not be read as “the universal current standard”, but as a good historical example for understanding the role of flags in a CPU.

For example, after computing A - B, the CPU checks the Z flag to know whether the result was zero, which is equivalent to A == B. A conditional branch instruction uses these flags to decide which instruction to execute next.

However, before it can calculate anything or check flags, the CPU must answer the most basic question when reading memory: “What does this sequence of zeros and ones mean?”. This is where the decoder comes into play.

The decoder

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The decoder is a combinational circuit of the \(n\)-to-\(2^n\) type: each combination of the opcode bits activates exactly one output, which corresponds to the operation to perform.

With 4 bits, for example, 16 outputs; with 8 bits, 256 outputs. Only the output corresponding to the received code is activated; the others remain inactive. This circuit is what turns the opcode bits into electrical signals that configure the ALU for the correct operation.

The ALU: Arithmetic Logic Unit

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Once the decoder has “translated” the instruction and prepared the electrical paths of the system, the stage is set for the processor’s brute force to act. The ALU obtains the data from the registers and deposits the results back into them. It is the ALU that does all the computational work proper:

The ALU does not access memory directly: it only operates on values that are already in the registers. It is up to the instruction cycle (next section) to ensure that the right data are in the right registers before the ALU operates.

The clock and the cycles

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The clock is a pulse generator that synchronizes all CPU operations. The frequency indicates how many cycles occur per second:

Each clock cycle can be subdivided into subcycles (\(t_0, t_1, t_2, \ldots, t_n\)), which correspond to internal microevents of the instruction cycle. The figure below shows this subdivision within the block diagram of the control unit: the clock pulses enter on one side, and each subcycle triggers one of the microevents that make up the execution of an instruction.

To get around the frequency limit and increase performance, processors have evolved their execution modes. Historically, CPUs operated in a strictly sequential mode (an instruction only started after the previous one finished). Today, we operate with concurrent execution (pipeline), where several instructions overlap in different stages (like an assembly line); parallel execution, with multiple cores processing instructions simultaneously; and vector execution, where a single instruction operates on multiple data at the same time.

The instruction cycle

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The CPU operates in a perpetual loop:

In practice, the choreography of this perpetual loop divides the CPU into two distinct roles. In the first stage, the processor acts as a reader looking for its next task; in the second, it becomes the executor:

The figure below shows a simplified flowchart of the instruction cycle, with the fetch, interpretation, and execution of an instruction.

Hardwired and microprogrammed control

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To generate the control signals of the instruction cycle, there are two classic approaches to designing the Control Unit:

• hardwired control: the signals are produced by fixed logic circuits; it tends to be faster, but also less flexible;
• microprogrammed control: the microoperations are described in an internal control memory; it tends to simplify the design of the CU, although it is normally slower than fully hardwired control.

This distinction matters because it shows that the CPU does not “understand” instructions by magic: it depends on an internal mechanism that translates each instruction into an organized sequence of control signals.

Microevents of the fetch cycle

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The fetch cycle unfolds into three consecutive micro-timings, described in RTL notation (the same one we used for memory operations in the article on the memory hierarchy):

Here, \(N\) represents the number of cells occupied by the instruction. In fixed-length instruction architectures, this increment is usually constant; in more complex architectures, it depends on the actual size of the fetched instruction.

Note that \(t_1\) has two simultaneous operations: the PC increment and the MM read can occur in parallel because they use distinct resources, the PC and the ALU (for the increment) versus the bus and the MM (for the read).

Instruction formats

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An instruction can contain a variable number of operands, depending on the architecture. The three main formats differ in how many explicit values the instruction references:

The 1-operand format is characteristic of accumulator architectures: the ACC is always one of the implicit operands, which simplifies the decoder circuit at the cost of less expressiveness per instruction.

The opcode size can be fixed (simpler and faster implementation, but it limits the number of operations) or variable (more flexible, more complex decoding). CISC architectures tend to use variable formats; RISC, fixed ones.

CISC vs. RISC

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This discussion about instruction design, whether formats should be variable and full of options or fixed and lean, created two schools of thought that clashed for decades:

The intuition behind CISC was to reduce the number of instructions needed to represent a program. The intuition behind RISC was to simplify the instructions to make execution faster and more predictable.

In practice, modern processors mix ideas from both schools: for example, the x86 family keeps a historically CISC interface, but internally translates the instructions into simpler micro-operations. This table is just the map of the territory. We will return to CISC and RISC in depth in the last article of the series, where the comparison gains data and the conclusion is less obvious than it seems.

The article after this one explores in detail how a hypothetical processor executes concrete instructions, step by step.

Practical examples

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With all the components in mind, we can size the registers and buses of a concrete machine from its specifications:

The next two examples combine concepts seen here with concepts of memory hierarchy and cache seen in the previous articles, showing how the design of the CPU and of the memory are interlinked.

Conclusion and next articles

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We now understand what the CPU is and how it is organized. We know each component (ALU, CU, registers, decoder, clock) and how the fetch cycle mobilizes them in sequence to bring an instruction from memory to the IR. But describing components and the fetch cycle is only half of the story. We have not yet seen what happens during the execute cycle: how the CPU actually processes a specific instruction, operating on concrete data.

In the next article, we will explore a hypothetical 12-bit processor with a limited instruction set. It will serve as a model for understanding the complete instruction cycle, the step-by-step execution of instructions such as LDA (load) and ADD (add), and the fundamentals of assembly, the low-level language that communicates directly with the hardware.

See you then!